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| PDSP16488A Single Chip 2D Convolver with Integral Line Delays Advance Information DS3713 ISSUE 6.4 December 1997 The PDSP16488A is a fully integrated, application specific, image processing device. It performs a two dimensional convolution between the pixels within a video window and a set of stored coefficients. An internal multiplier accumulator array can be multi-cycled at double or quadruple the pixel clock rate. This then gives the window size options listed in Table 1. An internal 32kbit RAM can be configured to provide either four or eight line delays. The length of each delay can be programmed to the users requirement, up to a maximum of 1024 pixels per line. The line delays are arranged in two groups,which may be internally connected in series or may be configured to accept separate pixel inputs. This allows interlaced video or frame to frame operations to be supported. The 8-bit coefficients are also stored internally and can be downloaded from a host computer or from an EPROM. No additional logic is required to support the EPROM and a single device can support up to 16 convolvers. The PDSP16488A contains an expansion adder and delay network which allows several devices to be cascaded. Convolvers with larger windows can then be fabricated as shown in Table 2. Intermediate 32-bit precision is provided to avoid any danger of overflow, but the final result will not normally occupy all bits. The PDSP16488A thus provides a gain control block in the output path, which allows the user to align the result to the most significant end of the 32-bit word. COMPOSITE DATA PIXEL CLOCK GEN SYNC ODD FIELD POWER EPROM ON ADDR DATA RESET CLK HRES BYPASS RES DELOP SYNC EXTRACT DELAYED SYNC PDSP16488A ADC OPTIONAL FIELD DELAY L7:0 D15:0 OUTPUT DATA IP7:0 Fig. 1 Typical stand-alone real time system Pixel Window size size Width Depth 8 8 8 16 16 4 8 8 4 8 4 4 8 4 4 Maximum pixel rate (MHz) 20 20 10 20 10 Line delays 431024 431024 83512 43512 43512 FEATURES s The PDSP16488A is a replacement for the PDSP16488 (see Note below) s 8 or 16-bit Pixels with rates up to 40 MHz s Window Sizes up to 838 with a Single Device s Eight Internal Line Delays s Supports Interlace and Frame-to-Frame Operations s Coefficients Supplied from an EPROM or Remote Host s Expandable in both X and Y for Larger Windows s Gain Control and Pixel Output Manipulation s 84-pin PGA or 132-pin QFP Package Options Note: PDSP16488A devices are not guaranteed to cascade with PDSP16488 devices. Zarlink Semiconductor do not recommend that PDSP16488A be mixed with PDSP16488 devices in a single equipment design. The PDSP16488A requires external pullup resistors in EPROM Mode (see Static Electrical Characteristics). Table 1 Single PDSP16488A configurations Max. No. of PDSP16488As for N3N window size pixel Pixel rate size 3 3 3 5 3 5 7 3 7 9 3 9 11311 15315 23323 (MHz) 10 10 20 20 40 40 8 16 8 16 8 16 1 1 1 1 1 2 1 2 2 4 4* 1 2 2 4 4* 4 6 4 6 4 8 9 - ORDERING INFORMATION Commercial (0C to 170C) PDSP16488A / C0 / AC (PGA) Industrial (240C to 185C) PDSP16488A / B0 / AC (PGA) PDSP16488A / B0 / GC (QFP) Military (255C to 1125C) PDSP16488A / A0 / AC (PGA) PDSP16488A / A0 / GC (QFP) PDSP16488A / MA / ACBR (PGA) MIL-STD-883 Class B* PDSP16488A / MA / GCPR (QFP) MIL-STD-883 Class B* *See Notes following Static Electrical CharacteristicsTable *Maximum rate is limited to 30MHz by line store expansion delays Table 2 PDSP16488As needed to implement typical window sizes PDSP16488A Signal IP7:0 L7:0 BYPASS HRES X15:0 D15:0 PC1 Type Input I/O Input Input Dual function Output Output Input Output I/O Input Description Pixel data input to the first line delay (most significant byte in 16-bit mode). Pixel data input to the second group of line delays. (least significant byte in 16-bit mode). Alternatively an output from the last line delay when the appropriate mode bit is set. The first line delay in the first group is bypassed when this input is high. No internal pullup resistor. Resets the line delay address pointers when high. Normally the composite sync signal in real time applications. In non real time systems it defines a frame store update period, when low. Address/data connections from a Master or Single device to the external coefficient source, with X15 defining EPROM or Host support. Otherwise they provide the expansion data input. Signed 16-bit scaled data or multiplexed 32-bit intermediate data. During intermediate transfers the most significant half is valid when the clock is low, and the least significant half when clock is high. During programming a Master device outputs a timing strobe on this pin. This is passed down the chain in a multiple device system, using the PC0 input on the next device. This pin is used in conjunction with PC1 in multiple device systems. It terminates the write strobe from a Master device which is EPROM supported. This output provides a version of the HRES input which has been delayed by an amount defined by the user. The data strobe from a host computer, active low. This pin will be an output from an EPROM supported Master device which provides strobes to the remaining devices. An active low enable which is internally gated with R/W and DS to perform reads or writes to the internal registers. In a Single or Master device, which is supported from an EPROM, the bottom 72 addresses are always used and CE is not needed. CE can then be used to initiate a new register load sequence after the power on load sequence. Read / not write line from the host CPU. When an EPROM is used this pin should be tied low. This pin is normally an input which signifies that registers are to be changed or examined. It is, however, an output from an EPROM supported Single or Master device indicating to the rest of the system that registers are being updated. Clock. All events are triggered on the rising edge of CLK, except the latching of least significant expansion inputs . Internally the clock can be multiplied by two or four in order to increase the effective number of multipliers. This output indicates the result from the internal comparison. A high value indicates that the pixel was greater than the internal threshold. The output is only valid from the last device in a chain. When high this output indicates that there has been a gain control overflow. Active low power on reset signal. Tied to ground to indicate a Single device system. Internal pullup resistor. Tied to ground to indicate the Master device in a multiple device system. Must be left open circuit in a Single device system. Internal pullup resistor. Output enable signal. Active low. Four address bits from a Master specifying one of sixteen devices in a multiple device system. Must be externally decoded to provide chip enables for the additional devices. These bits indicate the field selection given by the gain control auto select logic. The same coding as that used for Control Register bits C5:4 is used. 15V supply. All VDD pins must be connected. 0V supply. All GND pins must be connected. PC0 DELOP DS CE R/W Input I/O PROG CLK Input BIN OVR RES SINGLE MASTER Output Output Input Input Input Input Outputs Outputs Power Power OEN CS3:0 F1:0 VDD GND Table 3 Signal descriptions 2 PDSP16488A CE DS R/W PC0 PC1 RES CS3:0 BIDIRECTIONAL MULTIPURPOSE DATA BUS X15:0 PROG MASTER SINGLE DELOP HRES CONTROL IP7:0 Y DELAY COEFFICIENT STORE (64) X DELAY CONTROL REGISTERS BYPASS 1 LINE DELAY COMPARATOR BIN GAIN CONTROL 3 LINE DELAYS 838 ARRAY OF MACs 4 LINE DELAYS L7:0 Y DELAY ADDER OVR F1:0 MUX D15:0 CLK OEN Fig. 2 Functional block diagram 3 PDSP16488A A 1 2 3 4 5 6 7 8 9 10 11 12 13 B C D E F G H J K L M N Fig. 3a Pin connections for 84 I/O pin grid array package - AC84 (Power ) (bottom view) PIN 132 PIN 1 Fig 3b Pin connections for 132 I/O ceramic power flatpack - GC132 (Power) (top view) Fig 3 Pin connection diagrams (not to scale). See Table 3 for signal descriptions and Tables 4 and 5 for pinouts. 4 PDSP16488A Pin A1 B1 C2 C1 D2 D1 E2 E1 F2 G2 G1 H2 J1 J2 K1 K2 L1 Signal L0 F1 L1 L2 L3 N/C L4 L5 L6 L7 IP7 N/C IP6 IP5 IP4 N/C IP3 Pin L2 M1 N1 N2 M3 N3 M4 N4 M5 N5 M6 M7 N7 M8 N9 M9 N10 Signal IP2 IP1 IP0 BYPASS X15 X14 X13 N/C SINGLE Pin M10 N11 M11 N12 N13 M13 L12 L13 K12 K13 J12 J13 H12 G12 G13 F12 E13 Signal X5 X4 X3 X2 X1 X0 DELOP PC0 Pin E12 D13 D12 C13 C12 B13 A13 A12 B11 A11 B10 A10 B9 A9 B8 B7 A7 Signal HRES OVR PC1 Pin B6 A5 B5 A4 B4 A3 B3 A2 F1 N6 F13 A6 H1 N8 H13 A8 Signal D10 D11 N/C D12 D13 D14 D15 F0 VDD 1 VDD 2 VDD 3 VDD 4 GND1 GND2 GND3 GND4 BIN OEN RES X12 X11 MASTER X10 X9 X8 X7 X6 CS0 CS1 CS2 CS3 PROG DS CE R/W D0 D1 D2 D3 D4 D5 D6 D7 D8 CLK N/C D9 Table 4 Pin connections for AC84 (power) package. See Fig. 3a. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal N/C D0 OEN Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Signal N/C X2 X3 X4 N/C X5 GND X6 X7 N/C X8 X9 VDD VDD VDD X10 MASTER Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal N/C IP1 GND IP2 N/C VDD IP3 VDD IP4 GND IP5 GND IP6 VDD IP7 VDD N/C L7 GND L6 GND L5 VDD L4 VDD L3 VDD L2 GND L1 F1 L0 N/C Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Signal N/C VDD F0 D15 N/C D14 D13 GND D12 GND VDD VDD D11 D10 D9 GND CLK CLK CLK GND GND D8 VDD D7 D6 D5 D4 GND D3 N/C D2 D1 N/C BIN PC1 VDD GND OVR N/C HRES R/W CE N/C N/C GND N/C DS GND VDD PROG N/C X11 X12 SINGLE GND CS3 CS2 CS1 CS0 VDD RES PC0 N/C DELOP X0 X1 N/C GND GND N/C X13 X14 N/C X15 VDD BYPASS IP0 VDD N/C Table 5 Pin connections for GC132 (power) package. See Fig 3b. 5 PDSP16488A BASIC OPERATION The PDSP16488A convolver performs a weighted sum of all the pixels within an N3N two dimensional window. Each pixel value is multiplied by a signed coefficient, or weight, and the products are summed together. In practice positive weights would be used to produce averaging effects, with various distribution laws, and negative weights would be used for edge enhancement. The window is moved continuously over the video frame, and for real time operation a new result must be obtained for every pixel clock. In most applications odd sized windows will be used, resulting in a centre pixel whose value is modified by the surrounding pixels. effective number of multipliers, which are available to the user, from 16 to 32 or 64 respectively. This architecture produces a very efficient utilization of chip area, and allows the line delays to be accommodated on the same device. The sixteen multipliers are arranged in a 4 deep by 4 wide array, resulting in effective arrays of 4 by 8 or 8 by 8 with the multicycling options. The multiplier array can also be configured to handle 16-bit signed pixels; the effective number of available multipliers is then halved. Line Delay Operation Internal RAM is arranged in two separate groups, and can be configured to provide line delays to match the chosen size of the convolver. When a four deep arrangement is used, with 8-bit pixels, four line delays are available, and each can be programmed to contain up to 1024 pixels. In an eight deep array, or if 16-bit pixels are needed, each line can contain up to 512 pixels. Fig. 4 illustrates the options available. The first line delay in one of the groups can optionally be switched in or out under the control of an input pin. It is used to delay the pixel input when data is obtained from another convolver in a multiple device system, or it is used to support interlaced video. Signals L7:0 may be used as pixel inputs or outputs. They are configured as inputs at power-on to avoid possible bus conflicts, but by setting a mode control bit can become outputs. They can then be used to drive another device when multiple PDSP16488As are required. Output Accuracy With 8 bit pixels, and an 838 window, it is possible for the accumulated sum to grow to 22 bits within a single device. With 16-bit pixels, and an 834 window (the maximum possible), the sum can grow to 29 bits. The PDSP16488A actually allows for word growth up to 32 bits, and thus allows several devices to be cascaded without any danger of overflow. Since coefficients can be negative, the final result is a 32-bit signed two's complement number. In a particular application the desired output will lie somewhere within these 32 bits, the actual position being dependent on the coefficient values used. This causes problems in physically choosing which output pins to connect to the rest of the system. To overcome this problem the PDSP16488A contains a gain control block, which allows the final result to be aligned to the most significant end of the 32-bit internal result. The provision of the gain control block, rather than a simple shifter, allows the gain to be defined more accurately. The sixteen most significant bits of the adjusted result are available on output pins D15:0, which contains a sign bit. Interlaced Video When using real time interlaced video, a picture or frame is composed from two fields, with odd lines in one field and even lines in the other. An external field delay is thus required to gather information from adjacent lines, and the convolver needs two input buses. The bus providing the delayed pixels has an extra internal line delay. This is only used in the field containing the upper line in any pair of lines, and must be bypassed in the other field. It ensures that data from the previous field always corresponds to the line above the present active line, and avoids the need to change the position of the coefficients from one field to the next. Fig. 5 shows the translation from physical to internal line positions, for single device interlaced systems. Line N is the line presently being convolved, which is either one or two lines previous to the line presently being produced. When windows requiring four or more lines are to be implemented, the first line delay, in the group supplied from the L7:0 pins, must always be bypassed. This bypass option is controlled by register B, bit 7 and is not effected by the BYPASS input pin.. The coefficients must be loaded into the locations shown, which match the translated line positions, with unused coefficients, shown shaded, loaded with zeros. Output Saturation If the output from the convolver is driving a display, negative pixels will give erroneous results. An option is thus provided (register bits C7:6) that forces all negative results to zero, which are then interpreted as black by the display. At the same time positive results, which overflow the gain control, are forced to saturate at the most positive number, i.e. peak white. In this mode the output sign bit is always zero,and should not be connected to an A-D converter. A separate option forces both negative and positive overflows to saturate at their respective maximum values, but in scale negative results remain valid. A gain control overflow warning flag (OVR) is also available, which can be used in a host CPU supported system to change the gain parameters if overflows are not acceptable. Binary Output The PDSP16488A contains a 16-bit arithmetic comparator which allows the output from the gain control block to be compared with a previously programmed value. An output flag allows the user to detemine if the result was above or below a value contained within an internal register. Defining the Length of the Line Delay Fig. 5 defines the maximum line lengths available in each of the window size options. The actual line lengths can be defined in one of three ways, to support both real time applications, taking pixels directly from a camera, and also use in systems supported by a frame store. In the former case the line delays must be referenced to video synchronization pulses. In the latter case the line lengths are well defined, and the horizontal flyback `dead times' will have been removed. Multiplier Array The PDSP16488A contains sixteen 838 multipliers each producing a 16-bit result. Internally the pixel clock supplied by the user can be multiplied by two or four, which together with the proprietary architecture, allows each multiplier to be used several times within a pixel clock period. This increases the 6 PDSP16488A IP7:0 BYPASS 512 IP7:0 BYPASS 512 512 512 512 BYPASS 512 512 512 512 IP7:0 838 ARRAY L7:0 BYPASS 512 838 ARRAY BYPASS 512 16 512 512 512 512 L7:0 IP7:0 1024 BYPASS 512 512 512 L7:0 BYPASS 512 512 512 434 OR 834 16 ARRAY 16 16 IP7:0 BYPASS 512 1024 512 1024 1024 1024 L7:0 434 OR 834 ARRAY 1024 L7:0 1024 1024 434 OR 834 ARRAY 512 Fig. 4 Line delay configurations To support real time applications an option is provided in which the length of the line delay is defined by the number of clocks obtained while the HRES input is low. HRES would normally be composite sync when the convolver is directly attached to an NTSC or PAL video input. The line delay is achieved by reading the previous contents of a RAM-based line store, and then writing new information to the same address. When HRES is high, write operations are inhibited, and the address counter is reset. During an active line the counter is incremented by the pixel clock. If the maximum count is reached before the end of a line, then write operations are terminated and wraparound effects avoided. The rising edge of HRES, marking the end of a line, is normally asynchronous to the pixel clock, and it is possible for an additional pixel to be stored on some lines. This has no effect on the convolver operation, and will not cause a cumulative shift in the pixel position from line to line. An alternative means of defining the line length is, however, provided when an exact number of pixels is needed. HRES going low then starts the delay operation for every line, but it ceases when the 10-bit value contained in two registers is reached. This method can avoid the need to store blank pixels at the end of a line before HRES goes high. With this method the line must contain an even number of pixels but the value loaded into the control registers, defining the line length, must be one less than the even number required. In an image processing system, the pixel clock is often resynchronized, or even inhibited, during blanking or sync. The next line is then started with a precise time interval from the end of sync (falling edge of HRES) to the first pixel clock edge. This avoids any visible pixel jitter at the beginning of the line, which would otherwise be present since pixel clock is asynchronous with respect to video sync pulses. When using the PDSP16488A the pixel clock should not be inhibited, or re-synchronized, until the delayed version of the HRES input goes active. This is present on the DELOP output pin. This will ensure that no pixels on the right hand edge are lost due to the internal pipeline delay. If the pixel clock is a continuous signal, the user must ensure that the HRES high to low transition meets the timing requirements defined in Fig. 10. The HRES rising edge at the end of a line need not be synchronized. When pixels are read or written to a frame store, an alternative line delay configuration is needed. Within the frame store lines would be stored in contiguous locations, with no gaps caused by the flyback period between the lines. This method of use makes the HRES defined line delay operation difficult to use, and an alternative mode of operation is provided. The HRES input is then driven by a system-provided signal, which defines a complete frame store update period. It is not a line defining signal. The high to low transition of this signal will initiate the line store update sequence and allow the internal address pointers to increment. These pointers will be synchronously reset at the end of a line, when they reach the pre-programmed value. They will then immediately start a new operation using address zero. The actual line delay must be pre-loaded into two control registers as described previously. Write operations back to the frame store must allow for the total pipeline delay. This can be achieved by inhibiting write operations until DELOP goes low. Write operations then continue until it goes back high. The PDSP16488A assumes that data is valid when a clock signal is applied, and that it also meets the set up and hold requirements given in Fig. 10. If data is not valid due, for example, to a frame store DRAM refresh cycle, then the user must externally inhibit the clock. The clock supplied to the convolver will in this mode be a signal which defines a frame store cycle time. The use of the convolver in a line scan system is similar to its use with a frame store. These systems have no flyback period, and the address counter must be synchronously reset at the end of the line and then allowed to continue. 7 PDSP16488A 333 WINDOW LINE N21 LINE N LINE N11 C4 C8 C0 C5 C9 C1 C6 C10 C2 VIDEO LINE N12 FIELD DELAY L7:0 1024 1024 IP7:0 ODD FIELD 1024 N11 1024 N21 434 OR 834 N ARRAY Output is shifted by 1 line in every field 535 WINDOW LINE N22 LINE N21 LINE N LINE N11 LINE N12 C48 C8 C40 C0 C32 C49 C9 C41 C1 C33 C50 C10 C42 C2 C34 C51 C11 C43 C3 C35 C52 C12 FIELD DELAY IP7:0 ODD FIELD 512 N11 512 512 512 VIDEO LINE N12 L7:0 DELAY BYPASSED REG B BIT 7 SET 512 N12 512 512 512 N N22 N21 C44 C4 C36 838 ARRAY Output is shifted by 1 line in every field 838 WINDOW LINE N23 LINE N22 LINE N21 LINE N LINE N11 LINE N12 LINE N13 LINE N14 C24 C56 C16 C48 C8 C40 C0 C32 C25 C57 C17 C49 C9 C41 C1 C33 C26 C58 C18 C50 C10 C42 C2 C34 C27 C59 C19 C51 C11 C43 C3 C35 C28 C60 C20 C52 C12 C44 C4 C36 C29 C61 C21 C53 C13 C45 C5 C37 C30 C62 C22 C54 C14 C46 C6 C38 C31 C63 C23 C55 C15 C47 C7 C39 FIELD DELAY IP7:0 ODD FIELD 512 N13 512 512 512 VIDEO LINE N14 L7:0 DELAY BYPASSED REG B BIT 7 SET 512 N14 512 512 512 N12 N N22 N11 N21 N23 838 ARRAY Output is shifted by 2 lines in every field Fig. 5 Line delay allocations in SINGLE device interlaced systems 8 Gain Control Block This block is provided as an aid to locating the bits of interest in the 32-bit internal result. The magnitude of the largest convolved output will depend on the size of the window, and the coefficient values used. The function of the gain control block is then to produce an output, which is accurate to 16 bits, and which is aligned to the most significant end of this 32-bit word. The sixteen most significant bits of the word are available on D15:0 and the largest number need only have one sign bit if the gain control is correctly adjusted. Fig. 6 indicates the mechanism employed with the required function implemented in two steps. Two mode control bits, register C, bits 5:4, allow one of four 20 bit fields to be selected from the final 32-bit value. These four fields are positioned with the first at the most significant end, and then at four bit displacements down to the least significant end. By setting an enabling bit, register C, bit 0, the field selection can optionally be done automatically. This feature should only be used in the real time operating mode, when HRES defines video lines. Internal logic examines the most significant 13, 9, or 5 bits from the 32-bit result, and makes a field selection dependent on which group does not contain identical sign bits. If less than five sign bits are obtained, the logic will select the field containing the most significant 20 bits. The selection is indicated by F1:0. The automatic field selection is particularly useful when a fixed scene is being processed. The selection is reset when any internal register is updated (i.e. PROG has been low) and is then held high for ten further occurrences of the HRES input. This allows the internal multiplier/accumulator array to be completely flushed before a field selection is made. As convolver outputs of greater magnitude are produced the field selection logic will respond by selecting a more significant field. The most significant field found necessary remains selected until PROG again goes low. Even if the automatic field selection is not enabled, F1:0 will still indicate which field would have been selected. These are coded in the same way as register C, bits 5:4. Having chosen a field, either manually or automatically, it is then multiplied by a 4-bit unsigned integer. This is contained within the user-programmed gain control register, and the multiplication will produce a 24-bit result . The middle 16 bits of this result contain the required output bits. The gain control multiplier can overflow in to the unused most significant four bits if the parameters are chosen wrongly. This condition is flagged by pin OVR. By setting appropriate mode control bits, further manipulation of the gain control output is possible. One option, register C, bits FROM EXPANSION ADDER PDSP16488A 7:6 = 11, allows all negative outputs to be forced to zero, and at the same time positive gain control overflows will saturate at the maximum positive number. Register C, bits 7:6 = 10 will saturate positive and negative overflows at their respective maximum values, but otherwise leaves them unchanged. Occasional overflows can be tolerated in some systems, and this option prevents any gross errors. Expansion Multiple devices can be connected in cascade in order to obtain window sizes larger than those provided by a single PDSP16488A. This requires an additional adder in each device which is fed from expansion data inputs. This adder is not used by a Single device or the first device in a cascaded system, and is enabled or disabled by register B, bit 4. The first device in the cascaded system must be designated as a Master device by MASTER tying low. Its expansion input bus is then used as the source of data for the coefficient and control registers in all devices in the system. In order to reduce the pin count required for 32-bit buses, both expansion in and data out are time-multiplexed with the phases of the pixel clock. When the clock is high the least significant half will be valid, and when the clock is low the most significant half will be valid. In practice this multiplexing is only possible with pixel clocks up to 20MHz. Above these frequencies the multiplexing must be inhibited by setting register A, bit 7. The intermediate data accuracy will then be reduced, since only the lower 16 bits of the internal 32-bit intermediate sum are available on the D15:0 output pins. In such systems the coefficients must be scaled down in order to keep the intermediate and final results down to 16 bits. The final device should not use the gain control block but instead should simply output the non-multiplexed 16-bit result. The OVR flag and pixel saturation options will not be available. Pixel Input and Output Delays In a real time system, when line delays are referenced to video sync pulses present on the HRES input, the first pixel from the last line delay does not appear on the L7:0 pins until the fifth active pixel clock edge after HRES has gone low. This is illustrated in Fig. 8. In a vertically expanded system, this output provides the input to the first line delays in the vertically displaced devices. The internal logic is thus designed to always expect this five clock delay. Compensation must thus be applied to the devices which are directly connected to the video source, such that the first pixel is not valid until the fifth clock rising edge. For this reason the PDSP16488A contains an optional four clock pipeline delay on each of the pixel data inputs, as shown in Fig. 7. When the delay is used the first pixel in a video line must be available on the input pins after the first pixel clock edge. This would be so if the device were connected to an A-D converter, since that would introduce a one pixel pipeline delay. If the system introduces any further external pipeline delays, then the internal delay should be bypassed, and the user should ensure that the first pixel is valid after the fifth clock edge. The use of this four clock delay is controlled by register B, bit 3. This delay is in addition to the delays which are provided to support expansion in both the X and Y directions, and are controlled by register D, bits 3:2. Both delays are in fact simply added together in the device, but are separately defined since they add delays for different system reasons. AUTOMATIC FIELD SELECT F1:0 32 BITS MSB 20 12 4 20 8 8 20 4 MUX 20 24 4 16 4 16 SATURATE LOGIC 12 20 LSB D15:0 4 GAIN CONTROL REGISTER Fig. 6 Gain control block 9 PDSP16488A INPUT 0 REG B3 = 1 DELAYS PDSP16488A 0 REG B3 = 1 DELAYS Nth PDSP16488A IN THE ROW 0 DELAY = 0, DEFINED BY REG D3:2 = 00 DELAYS WIDTH = S LINE DELAYS ZERO 4 CLOCK DELAYS 0 DELAY = 0, DEFINED BY REG D3:2 = 00 DELAYS WIDTH = S LINE DELAYS 0 DELAYS REG D0 = 0 + 4 CLOCK DELAY 0/4 DELAYS REG D0 = 0 IF S = 4, OR REG D0 = 1 IF S = 8 + 4 CLOCK DELAY 0 REG B3 = 0 DELAYS PDSP16488A 0 REG B3 = 1 DELAYS Nth PDSP16488A IN THE ROW D D = 41S(N21) DEFINED BY REG D3:2 DELAYS WIDTH = S LINE DELAYS D D = 41S(N21) DEFINED BY REG D3:2 DELAYS WIDTH = S LINE DELAYS 0 DELAYS 4 CLOCK DELAYS REG D0 = 0 + 4 CLOCK DELAY 0/4 DELAYS REG D0 = 0 IF S = 4, OR REG D0 = 1 IF S = 8 + 4 CLOCK DELAY 0 REG B3 = 0 DELAYS PDSP16488A 0 REG B3 = 1 DELAYS Nth PDSP16488A IN THE ROW D D = 41S(N21) DEFINED BY REG D3:2 DELAYS WIDTH = S LINE DELAYS D DELAYS D = 41S(N21) DEFINED BY REG D3:2 WIDTH = S LINE DELAYS 0 DELAYS REG D0 = 0 + 4 CLOCK DELAY 0/4 DELAYS REG D0 = 0 IF S = 4, OR REG D0 = 1 IF S = 8 + 4 CLOCK DELAY OUTPUT Fig. 7 Multi-device delay paths Delay Compensation for Large Windows A large window is composed of several partial windows each of which is implemented in an individual device. If necessary the partial window must be padded with zero coefficients to become one of the standard sizes. When constructing a large window it is necessary to delay the expansion data inputs in order to compensate for growth in the horizontal direction. Delays in the partial sums are also necessary to compensate for the total pipeline delay needed to produce the previous complete horizontal stripe. Within each device in a horizontal stripe, apart from the first, the expansion input must be delayed by the width of the partial window, before it is added to the internal sum. Since partial windows can only be 4 or 8 pixels wide, a delay of 4 or 8 pixel clocks is needed. There is, however, an in-built delay of 4 pixels in the inter device connection, and the PDSP16488A thus only needs an option to delay the expansion input by an additional four pixels. 10 The data from the last device in a horizontal row of convolvers feeds the expansion input of the first device in the next row. This is shown in Fig. 7. With this arrangement, the position of the partial window as illustrated, is the inverse of its vertical position on a normal TV screen. Thus the top left hand device corresponds to the bottom left hand portion of the complete window. The output from the last device in the row is delayed with respect to the original data input by an amount given by the formula; DELAY = 41S(N21), where N is the number of devices in a row and S is the partial window width, i.e. 4 or 8. The internal convolver sums, in each of the devices in the next row, must be delayed by this amount before they are added to results from the previous row. This is more conveniently achieved by delaying data going into the line stores. The required cumulative delay with respect to the first horizontal stripe is then automatically obtained when more than two rows of devices are needed. Register D, bits 3:2 are used to define one of four delay options. These delays have been selected to support systems needing from two to eight devices and are described in the applications section. PDSP16488A Function Mode Reg A Mode Reg B Mode Reg C Mode Reg D Comparator LSB Comparator MSB Scale value Pixels/line LSB Pixels/line MSB C0-C15 C16-C31 C32-C47 C48-C63 Unused Hex address 00 01 02 03 04 05 06 07 08 40-4F 50-5F 60-6F 70-7F 09-3F Table 5 Internal register addressing Data size 8 8 8 15 16 Window size 43 4 83 4 83 8 43 4 83 4 Table 6 Pipeline delays Pipeline delay 34 30 26 28 26 Coefficients Sixty-four coefficients are stored internally and must be initially loaded from an external source. Table 5 gives the coefficient addresses within a device, with coefficient C0 specified by the least significant address and C63 by the most significant address. Fig. 9 shows the physical window position within the device that is allocated to each coefficient in the various modes of operation. Horizontally the coefficient positions correspond to the convolution process as if it were observed on a viewing screen, i.e. the left hand pixel is multiplied with C0. In the vertical direction the lines of coefficients are inverted with respect to a visual screen, i.e. the line starting with C0 is actually at the bottom of the visualized window. The coefficients may be provided from a Host CPU using conventional addressing, a read/not write line, data strobe, and a chip enable. Alternatively, in stand alone systems, an EPROM may be used. A single EPROM can support up to 16 devices with no additional hardware. When windows are to be fabricated which are smaller than the maximum size that the device will provide in the required configuration, then the areas which are not to be used must contain zero coefficients. The pipeline delay will then be that of a completely filled window. Total Pipeline Delay The total pipeline delay is dependent on the device configuration and the number of devices in the system. Table 6 gives the delays obtained with the various single device configurations when the gain control is used. These delays are the internal processing delays and do not include the delays needed to move a given size window completely into a field of interest. When multiple devices are needed, additional delays are produced which must be calculated for the particular application. These delays are discussed in the applications section. The PDSP16488A contains facilities for outputting a delayed version of HRES (DELOP) to match any processing delay. Register C. bits 3:1 allow this delay to be selected from any value between 29 and 92 pixel clocks as detailed in Table 9. ACTIVE LINE PERIOD tRSU HRES (sync) 2 3 4 5 6 7 8 ASYNCHRONOUS BACK EDGE 1 2 6 7 CLK FIRST PIXEL VALID (REG B3 SET) FIRST PIXEL FROM LINE STORE VALID LAST2 PIXELS INTERNALLY STORED LINE STORE WRITES INHIBITED Fig.8 Pixel input delays 11 PDSP16488A IP7:0 512 C0 512 C1 C9 C17 C25 C33 C41 C49 C57 C2 C10 C18 C26 C34 C42 C50 C58 C3 C11 C19 C27 C35 C43 C51 C59 C4 C12 C20 C28 C36 C44 C52 C60 C5 C13 C21 C29 C37 C45 C53 C61 C6 C14 C22 C30 C38 C46 C54 C62 C7 C15 C23 C31 C39 C47 C55 C63 C8 512 C16 512 C24 512 C32 512 C40 512 C48 512 C56 L7:0 IP7:0 L7:0 838, 8-BIT DATA 512 MSB 512 512 512 512 LSB 16 512 512 512 16 16 16 C0 C1 C32 C33 C8 C9 C40 C41 C16 C17 C48 C49 C24 C25 C56 C57 C2 C3 C34 C35 C10 C11 C42 C43 C18 C19 C50 C51 C26 C27 C58 C59 C4 C36 C12 C44 C20 C52 C28 C60 C5 C37 C13 C45 C21 C53 C29 C61 C6 C7 C38 C39 C14 C15 C46 C47 C22 C23 C54 C55 C30 C31 C62 C63 834, 16-BIT DATA IP7:0 1024 C0 1024 C1 C9 C17 C25 C2 C10 C18 C26 C3 C11 C19 C27 C4 C12 C20 C28 C5 C13 C21 C29 C6 C14 C22 C30 C7 C15 C23 C31 IP7:0 C8 1024 C16 1024 C24 IP7:0 L7:0 L7:0 834, 8-BIT DATA 512 MSB 512 512 512 512 LSB 16 512 512 512 16 16 16 1024 C0 C1 C16 C17 C4 C5 C20 C21 C8 C9 C24 C25 C12 C13 C28 C29 C2 C3 C18 C19 C6 C7 C22 C23 C10 C11 C26 C27 C14 C15 C30 C31 1024 C0 C4 1024 C1 C5 C9 C13 C2 C6 C10 C14 C3 C7 C11 C15 C8 1024 C12 L7:0 434, 16-BIT DATA 434, 8-BIT DATA NOTE: Two coefficients occurring in the same box have identical values Fig. 9 Physical coefficient positions 12 Loading Registers from a Host CPU The X14:0 expansion data inputs on a single or master device are connected to the host bus to provide address and data for the internal registers. In a multiple device system the remaining devices receive addresses and data which have been passed through the expansion connection between earlier devices in the cascade chain. Each device needs an individual chip enable ( CE) plus a global data strobe ( DS), a read/ not write ( R/W) line, and PROG signal from the host. Registers are individually addressed and can be loaded in any sequence once the global PROG signal has been produced by the host. The latter would normally be produced from an address decoder encompassing all the necessary device addresses. If a self-timed system is to be implemented, a timing strobe must be passed down the expansion chain through the PC0/PC1 connections. The PC0 output from the final device is used as a host R E P LY signal, and indicates that the last device has received data after the propagation delay of previous devices. The timing strobe is produced in the Master device from the host data strobe, and will appear on the PC0 output. This feature allows the user to cascade any number of devices without having to know the propagation delay through each device. The timing information for this mode of operation is given in Fig. 10. The host can also read the data contained in the internal registers. The required device is selected using chip enable with the R/W line high, indicating a read operation. Single device systems output the data read on X7:0, but in multiple device systems data is read from the D7:0 outputs on the final device in the chain. These must be connected back to the host data bus through tristate drivers, whose tristate control must be generated externally (see Figs. 14 and 15). When earlier devices in the chain are addressed, the register contents are transferred through the expansion connections down to the final device. In the self timed configuration the data will be valid when REPLY is taken low by PC1 , as shown in Fig. 10. If R E P LY is not to be used, the PC0/PC1 connections are not necessary, and the host data strobe for a write operation must be wide enough to allow for the worst case propagation delay through all the devices (tDEL). If the data or address from the host does not meet the set up time given in Fig. 8, the width of the data strobe can be simply extended to compensate for the additional delay. When reading data the access time required is tACC1tDEL(N21), using the maximum times given in the Host Mode Switching Characteristics. Host control lines X7:0 8-bit data bus. In a Single device system this bus is bidirectional; in other configurations it is an input. Only a Single or Master device is connected directly to the host. Other devices receive data from the output of the previous device in the chain. X14:8 7-bit address bus which is used to identify one of the 73 internal registers. Connected in the same manner as X7:0. X15 must be open circuit on the Master device An input from the previous PC1 output in a multiple device chain. Not needed on a Single device or if the self timed feature is not used. Reply to the host from a Single device or from the last device in a cascade chain. It indicates that the write strobe can be terminated. Connected to PC0 input of the next device at intermediate points in the chain if the self timed feature is used. R/W PDSP16488A Read/Not Write line from the host CPU which is connected to all devices in the system. An active low enable which is normally produced from a global address decode for the particular device. This must encompass all internal register addresses. An active low host data strobe which is connected to all devices in the system. An active low global signal, produced by the host, which is connected to all devices in the system. Together with a unique chip enable for every device, it allows the internal registers to be updated or examined by the host PROG and CE should be tied together in a Single device system. CE DS PROG Loading Registers from an EPROM In the EPROM mode, one device has to assume the role of a host computer. If more than one device is present, this must be the first component in the chain, which must have its MASTER pin tied low. The Master device contains internal address counters which allow the registers in up to 16 cascaded PDSP16488As to be specified. It also generates the PROG signal and a data strobe on the pins which were previously inputs. These outputs must be connected to the other devices in the system, which still use them as inputs. The R/W input should be tied low on all devices. The width of the data strobe is determined by the feedback connection from the PC1 output on the last device to the PC0 input on the Master. The PC0/PC1 connections must be made between devices in a multiple device system; in a single device system the connection is made internally. The available EPROM access time is determined by an internal oscillator and does not require the pixel clock to be present during the programming sequence. Any pixel clock resynchronization in a real time system will thus not affect the coefficient load operation. The relevant EPROM timing information is shown in Fig. 11. The load procedure will commence after RES has gone from low to high, and will be indicated by the PROG output going low. The data from 73 EPROM locations will be loaded into the internal registers using addresses corresponding to those in Table 5. Within a particular page of 128 EPROM locations, the first nine locations supply control register information, and the top 64 supply coefficients. The middle 55 locations are not used. If the window size is 834, the top 32 locations will also contain redundant data, and if the size is 434 the top 48 will be redundant. In a multiple device system the load sequence will be repeated for every device, and four additional address bits will be generated on the CS3:0 pins. These address bits provide the EPROM with a page address, with one page allocated to each device in the system. Within each page only 73 locations provide data for a convolver, the remainder are redundant as in the single device system. The CS3:0 outputs must also be decoded in order to provide individual chip enables for each device. These can readily be derived by using an AS138 TTL decoder. Bits in an internal control register determine the number of times that the sequence is repeated. If changes to the convolver operation are to be made after power-on, activating the CE input on the Master or Single device will instigate the load procedure. Additional EPROM address bits supplied from the system will allow different filter coefficients to be used. X15 PC0 PC1 13 EPROM control lines X7:0 8 bit data from the EPROM to the Master or Single device. Otherwise data is received from the previous device in the chain. X14:8 Lower 7 address bits to the EPROM from a Master or Single device. Otherwise an input from the data output of the previous device. Tied to ground on a Master device to indicate the EPROM mode. Tied low on all devices. An output from a Master or Single device which provides a data strobe for the other devices. A pullup resistor is required on this pin in EPROM mode Four additional address bits for the EPROM which are provided by the Master device. They allow 16 additional devices to be used and must be externally decoded to provide chip enables. An input on the Master device which is driven from the PC1 output of the last device in the chain. Used internally to terminate the write strobe. Connected to previous PC1 outputs at intermediate points in the chain. Not needed for a Single device. An output connected to the PC0 input of the next device in the chain. The last device feeds back to the Master. Not needed for a Single device. An enable which is produced by decoding CS3:0 from the Master. It is not needed for a Master or Single device which will always use the bottom block of addresses with internally generated write strobes. It can, however, be used on these devices to initiate a new load procedure after the initial power-on sequence. An active low signal produced by an EPROM supported Master or Single device. An input to all other devices. It indicates that a register load sequence is occurring, either after power on, or as the result of CE as explained above. It remains active until register 73 in the final device has been loaded. Register A, bits 3:0 define the number of cascaded devices. A pullup resistor is required on this pin in EPROM mode. PDSP16488A cease when the value in the counter equals that contained in these bits. The bits are redundant in a Single device which only uses one 128-byte block. BITS 6:4 These bits define one of the five basic configurations. The line delays will automatically be configured to match the chosen window size and pixel accuracy. The maximum clock rate that is available to the user reflects the internal multiplication factor. BIT 7 This bit must be set if the pixel clock is greater than 20MHz. It disables the output and input time multiplexing, and instead outputs the least significant half of the 32-bit intermediate sum for the complete clock cycle. When the gain control is used, the output multiplexing will automatically be disabled. X15 R/W DS CS3: 0 Bit 3:0 6:4 6:4 6:4 6:4 6:4 7 7 Code XXXX 000 001 010 011 101 0 1 Function Number of extra devices from 1-15 8-bit, 838 window, 10MHz max., 83512 line delays. 16-bit, 834 window, 10MHz max., 43512 line delays. 16-bit, 434 window, 20MHz max., 43512 line delays. 8-bit, 834 window, 20MHz max., 431024 line delays. 8-bit, 434 window, 40MHz max., 431024 line delays Multiplexed exp. data Non-multiplexed exp. data PC0 PC1 CE Table 8 Register A bit functions PROG Register B bit allocation (Table 9) BIT 0 This bit defines the input for the second group of line delays. It must be set in the 16-bit pixel modes, and is set by power on reset. BIT 2:1 These bits control the mode of operation of the line stores. In real time systems pixels can be stored either until HRES (sync) goes high , or until a predetermined count is reached. In the frame store mode line store operations are continuous, with a pre-determined line length. When this bit is set four pipeline delays are added to the pixel inputs to compensate for the internal/ external delays between line stores. The extra delay is only necessary when a device supplied with system video in which the first pixel in a line is valid in the period following the first active clock edge. See Fig 7. The delay is not necessary if the device is fed from the output of another convolver. When set this bit will add four additional delays to those defined by register D, bits 4: 2. When this bit is set the expansion adder will not be used. It is automatically set in a Master or Single device. System Configuration The device is configured using a combination of the state of the S I N G L E and MASTER pins, and the contents of the four Mode Control registers. In a Master or Single device the state of the X15 pin is used to define whether the system is EPROM or Host supported, as described above. BIT 3 Mode Control Registers Register A bit allocation (Table 8) BITS 3:0 These bits are `don't care' when using a host computer but to a Master device, in an EPROM supported system, they define the number of interconnected chips. The EPROM must contain contiguous 128 byte blocks for each of the devices in the system and a 4bit counter in the Master device will sequence through up to 16 block reads. An internal comparator in the Master causes the loading of the internal registers to BIT 4 14 BIT 7 This bit controls the bypass option on the first line delay on the L7:0 inputs. It is only effective when an 8 bit pixel mode is selected, which also needs more than four line delays. When L7:0 are used as outputs it should always be reset. In the 16-bit modes the bypass function is only controlled by the BYPASS pin, and the bit is redundant. Code 0 1 00 01 10 11 0 1 0 1 0 1 Function Second line delay group fed from the first group Second line delay group fed from L7:0 which become inputs Store pixels to end of line Store pixels till count is reached Frame store operation Not Used No delays on pixel inputs 4 delays on both pixel inputs Use expansion adder Expansion adder disabled Not used Use first delay in second group Bypass first delay in second group PDSP16488A Bit 3:1 3:1 3:1 3:1 3:1 5:4 5:4 5:4 5:4 7:6 7:6 7:6 7:6 Code 011 100 101 110 111 00 01 10 11 00 01 10 11 Function DELOP = 29124 clocks DELOP = 29132 clocks DELOP = 29140 clocks DELOP = 29148 clocks DELOP = 29156 clocks Select upper 20 bits Select next 20 bits Select next 20 bits Select bottom 20 bits By-pass the gain control Normal gain control output Saturate at max.1ve and 2ve values. Force 2ve to zero.Sat.1ve values. Bit 0 0 2:1 2:1 2:1 2:1 3 3 4 4 6:5 7 7 Table 10 Register C bit functions (continued) Register D bit allocation (Table 11) BIT 0 If this bit is set the expansion data input is delayed by four pixel clocks before it is added to the present convolver output. It is used in multiple device systems when the partial window width is 8 pixels. BIT 1 When this bit is set the internal sum is shifted to the left by 8 places before being added to the expansion input. It is used when two devices are used, each in an 8-bit pixel mode, to construct a 16-bit pixel mode. Table 9 Register B bit functions Register C bit allocation (Table 10) BIT 0 If this bit is set, the 20-bit field selected from the 32-bit result, is defined automatically by internal logic. BITS 3:1 These bits are in conjunction with register D, bits 7:5 to define the pixel delay from the HRES input to the DELOP output. They are used to match the appropriate processing delay in a particular system. The minimum delay is 29 pixel clocks. BITS 5:4 These bits define which of the four 20-bit fields out of the 32-bit final result is selected as the input to the gain control. They are redundant when the gain control is not used, or if register C, bit 0, is set. BITS 7:6 These bits define the use of the gain control as given in Table 10. Intermediate devices in a multiple device system must bypass the gain control block, otherwise the additional pipeline delays will affect the result. Disabling the gain control block will reduce the device pipeline by 13 CLK cycles from the delays shown in Table 6. Bit 0 0 3:1 3:1 3:1 Code 0 1 000 001 010 Function Field selection defined by C5:4 Automatic field selection DELOP = 2910 clocks DELOP = 2918 clocks DELOP = 29116 clocks BITS 3:2 These bits define the delays on both sets of pixel inputs before entering the line stores. The delays are always identical on both sets. BIT 4 BIT 7:5 When this bit is set the convolver interprets 8 or 16bit pixels as 2's complement signed numbers These bits add 0 to 7 additional clock delays to those selected by Register C, bits 3:1. Bit 0 0 1 1 3:2 3:2 3:2 3:2 4 4 7:5 Code 0 1 0 1 00 01 10 11 0 1 XXX Function X15:0 Not delayed X15:0 Delayed Internal sum not shifted Internal sum multiplied by 256 Input to line stores not delayed Input to line stores delayed by 4 Input to line stores delayed by 8 Input to line stores delayed by 12 Unsigned pixel data input 2's complement pixel data input Add 0 to 7 clock delays to DELOP Table 10 Register C bit functions (continues...) Table 11 Register D bit functions 15 PDSP16488A ELECTRICAL CHARACTERISTICS The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated: VDD = 15V10%, GND = 0V, T AMB (Commercial) = 0C to170C, T AMB (Industrial) = 240C to 185C, TAMB (Military) = 255C to 1125C Static Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current Input capacitance Output leakage current Output short circuit current Current at full speed Symbol Min. VOH VOL VIH VIL IIN CIN IOZ IOS ISP 2*4 2*0 2 10 10 2 50 10 1 50 300 Max. Value Typ. Max. 0*4 0*8 1 10 V V V V A pF A mA mA IOH = 4mA IOL = 28mA Units Conditions GND < VIN < VDD, no internal pullup GND < VOUT < VDD , no internal pullup VDD = 15*5V NOTE: Signal pins PC0, X15, MASTER, SINGLE and OVR have pullup resistors in the range 15k to 200k. BYPASS, PROG and DS have no internal pullup resistors. When the device is used in EPROM mode, external pullup resistors should be connected to the PROG and DS pins. ABSOLUTE MAXIMUM RATINGS (NOTE 1) Supply voltage, V DD 20*5V to 17*0V 20*5V to VDD 10*5V Input voltage, VIN 20*5V to VDD 10*5V Output voltage, VOUT 18mA Clamp diode current per pin, I K (see note 2) 500V Static discharge voltage (HBM) Storage temperature, TS 265C to1150C Maximum junction temperature, TJMAX Commercial grade 195C Industrial grade 1110C Military grade 1150C Package power dissipation 2000mW Thermal resistance, junction-to-case, JC 5C/W NOTES 1. Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. 2. Maximum dissipation should not be exceeded for more than1 second, only one output to be tested at any one time. 3. Exposure to absolute maximum ratings for extended periods may affect device reliablity. 4. Current is defined as negative into the device. Polyimide is used as an inter-layer dielectric and as glassification. Polymeric material is also used for die attach which, according to the requirements in paragraph 1.2.1, precludes categorising these devices as fully compliant. In every other respect, these devices are manufactured and screened in full accordance with MIL-STD-883 (latest revision). The PDSP16488A MA ACBR (PGA packge) is subject to the constant acceleration test, Method 2001, Test Condition A (5kg). Life test/burn-in connections are given in Tables 12 and 13 on the following page. PDSP16488A MA ACBR and PDSP16488A MA GCPR (MIL-STD-883 CLASS B PARTS) Change Notification The change notification requirements of MIL-PRF-38535 will be implemented on MIL-STD-883 grade devices. Known customers will be notified of any changes since the last buy when ordering further parts if significant changes have been made. Rev. Date A MAR 1993 B JUL 1996 C NOV 1997 D 16 PDSP16488A Pin A1 B1 C2 C1 D2 D1 E2 E1 F2 G2 G1 H2 J1 J2 K1 K2 L1 Voltage GND N/C GND GND GND N/C GND GND GND GND 1 5*0V N/C 1 5*0V 1 5*0V 1 5*0V N/C GND Pin L2 M1 N1 N2 M3 N3 M4 N4 M5 N5 M6 M7 N7 M8 N9 M9 N10 Voltage GND GND GND GND N/C N/C N/C N/C 1 5*0V N/C N/C 1 5*0V N/C N/C N/C N/C N/C Pin M10 N11 M11 N12 N13 M13 L12 L13 K12 K13 J12 J13 H12 G12 G13 F12 E13 Voltage N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C GND 15*0V 15*0V GND Pin E12 D13 D12 C13 C12 B13 A13 A12 B11 A11 B10 A10 B9 A9 B8 B7 A7 Voltage 15*0V N/C N/C N/C 15*0V N/C N/C N/C N/C N/C N/C N/C N/C N/C 15*0V N/C N/C Pin B6 A5 B5 A4 B4 A3 B3 A2 F1 N6 F13 A6 H1 N8 H13 A8 Voltage N/C N/C N/C N/C N/C N/C N/C N/C 1 5*0V 1 5*0V 1 5*0V 1 5*0V GND GND GND GND Table 12 Life test/burn-in connections for PDSP16488A MA ACBR (PGA). NOTE: PDA is 5% and based on groups 1 and 7 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Voltage N/C N/C 15*0V N/C N/C 15*0V GND N/C N/C 15*0V GND 15*0V N/C N/C N/C N/C 15*0V GND N/C GND GND N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Voltage N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C 1 5*0V N/C 1 5*0V N/C 1 5*0V N/C N/C N/C 1 5*0V GND GND N/C N/C N/C N/C N/C N/C GND GND N/C N/C Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Voltage N/C GND N/C GND N/C 15*0V GND 15*0V 15*0V GND 15*0V GND 15*0V 15*0V 15*0V 15*0V N/C GND GND GND GND GND 15*0V GND 15*0V GND 15*0V GND GND GND N/C GND N/C Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Voltage N/C 1 5*0V N/C N/C N/C N/C N/C GND N/C GND N/C 1 5*0V N/C N/C N/C GND N/C N/C N/C GND GND N/C 1 5*0V N/C N/C N/C N/C GND N/C N/C N/C N/C N/C Table 13 Life test/burn-in connections for PDSP16488A MA GCPR (QFP). NOTE: PDA is 5% and based on groups 1 and 7 17 PDSP16488Afor Host mode Switching Characteristics Characteristic DS hold time after R E P LY low Host address/data setup time Read setup time to prevent Write Host signal hold time Expansion in to data out in PROG mode Delay from DS low to PC1 low (Note 2) CE setup time CE hold time PROG setup time PROG hold time PC1 high delay after DS high Coefficient read time Coefficients valid time before REPLY Symbol tDSH tHSU tRA tHH tDEL tEXP tCSU tCH tPSU tPH tPCH tACC tRSU Value Min. 20 0 5 10 30 50 0 0 0 0 50 50 5 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Only applicable for Read ops and if REPLY is used Only applicable if REPLY is used (Note 1) Must always be guaranteed No clocks are needed in PROG mode Greater than tDEL under all conditions Defines DS high time From Master or Single device NOTES 1. If REPLY is not used, time is referenced to the rising edge of DS and when set up must be N3tDEL for N devices. 2. Equivalent to PC0 to PC1 delay DATUM tWAIT > tPCH DS tCSU CE tPSU PROG tACC COEFFICIENT OUTPUT, X7:0 tEXP tRSU PC1 FROM MASTER OR SINGLE DEVICE tDSH PC1 FROM LAST DEVICE (REPLY) tRA R/W FROM HOST tHSU ADDRESS/DATA FROM HOST tDEL HOST DATA OUTPUT FROM FIRST DEVICE VALID VALID tCH tPH tPCH tHH Fig. 10 Host timing 18 Switching Characteristics for EPROM mode Characteristic Delay from DS low to Master PC1 Delay from PC0 low to DS high Delay from DS high to PC1 high DS high time DS high to new EPROM address EPROM data setup time DS low time CE setup time CE hold time EPROM data access time Expansion in to data out PC0 to PC1 delay Symbol tPCD tWH tPCH tWW tAD tDS tRW tCSU tCH tDA tDEL tEXP Value Min. Max. 50 5 50 250 30 20 10 0 0 200 30 50 ns ns ns ns ns ns ns ns ns ns ns ns Units PDSP16488A Conditions Single device Greater than tDEL at all temperatures tRW tWH DS FROM MASTER tPCD PC1 FROM MASTER tEXP PC1 FROM NEXT DEVICE tWW tPCH PC1 FROM LAST DEVICE (PC0 TO MASTER) EPROM ADDRESS VALID tAD VALID tDA EPROM DATA tDS VALID tCSU CE tCH DATA OUTPUT FROM FIRST DEVICE tDEL VALID tDEL DATA OUTPUT FROM SECOND DEVICE VALID Fig. 11 EPROM timing 19 PDSP16488A operational timings Switching Characteristics, Characteristic CLK low time CLK high time Data in setup time Data in hold time CLK rising to output delay L7:0 output delay HRES low setup time Output enable time Output disable time X15:0 Expansion setup time X15:0 Expansion hold time Symbol tCL tCH tDSU tDH tRD tLD tRSU tDLZ tDHZ tXSU tXDH Value Min. 25 10 25 10 10 0 21 20 10 15 15 5 7 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns 32-bit multiplexed output 16-bit output 32-bit multiplexed output 16-bit output Units Conditions Increase to 24ns for DELOP output tCH CLK tLD L7:0 LINE STORE OUTPUTS tRSU HRES VALID OEN tRD DATA AND FLAG OUTPUTS tDSU PIXEL DATA IN tDH tDHZ HIGH Z (D15:0 ONLY) VALID tXSU X15:0 DATA IN tXDH VALID Fig. 12 Operational timing 20 Measured with a 15k series resistor and 30pF load capacitance tCL tDLZ tXSU tXDH VALID VALID APPLICATIONS INFORMATION Device Requirements The number of devices required to implement a given convolver window depends on the size of the window, the required pixel rate, and whether the pixel accuracy is to be 8 or 16 bits. In practice the PDSP16488A supports windows requiring one, two, four, six, or eight devices without additional logic. Table 2 gives typical window sizes which may be obtained with the above number of devices. Figs. 13 through 20 show system interconnections for these arrangements. Other configurations are possible but may need the support of additional pixel/line delays and/or expansion adders. Although not necessarily shown, all configurations can be supported by either an EPROM or a Host computer. Interlaced or non-interlaced video may also be used, unless explicitly stated otherwise in the text. Expansion with 8-bit pixels is a straightforward process and the number of devices needed is easily deduced from the window sizes available in a single device. At pixel rates above 20MHz it may not be practical to use more than four devices, since the full 32-bit intermediate precision is not available. The lack of expansion multiplexing reduces the intermediate precision to 16 bits. The partial sum outputs must thus not overflow these 16 bits; this will require the coefficients to be scaled down appropriately with a resulting loss in accuracy. Expansion with 16-bit pixels can be achieved in several ways. The simplest way is to use two devices, each working with 8-bit pixels. One device handles the least significant part of the data, and its output feeds the expansion input of a second device. This performs the most significant half of the calculation. The least significant half is then added to the most significant sum, after the latter has been multiplied by 256, i.e. shifted by eight places. This shift is done internally and controlled by Register D, bit 1. The internal 32-bit accuracy prevents any loss in precision due the shift and add operation. The window size with this arrangement is restricted to that available in a single device, at the required pixel rate but with 8-bit pixels. Thus two devices can be used, for example, to provide an 838 window with 16-bit pixels and 10MHz rates. If a larger extended precision window is needed, it is possible to use four devices. Each device is then programmed to be in a 16-bit data mode, but should be restricted to rates below 20MHz, if the 32-bit intermediate precision is to be maintained. In the 16bit modes, however, the output from the last line delay is not available due to pin limitations. This is not a problem in a four device interlaced system, since half of the devices will be fed from an external field delay. In non interlaced systems additional external line delays would be needed. An alternative approach would be to configure all the devices in the appropriate 8-bit mode, do separate least significant and most significant calculations, and then combine the results in an external adder after a wired-in shift. Single device configuration Fig.13 illustrates both EPROM and Host supported single device systems, with or without interlaced video. In both cases the Single and X15 pins must be tied low, and the PC0 , PC1 , and DS pins are redundant. The PROG pin becomes an output and indicates that a register load sequence is occurring. The first line delay must always be bypassed in a non interlaced system, however, since an internal pullup is not provided, the BYPASS pin should be tied to VCC for the correct operation. With interlaced video the BYPASS input is used to distinguish between the odd and even fields. The CE input may be left open circuit if coefficients are to be simply loaded after a power on reset signal; the latter being applied to the RES input. Alternatively the CE input may be used to change the coefficients at any time after power on reset; the EPROM would then need additional address bits for the extra sets of coefficients that are to be stored. PDSP16488A In an interlaced system the pixels from the previous field must use the IP7:0 inputs, and the live pixels must use the L7:0 inputs. Interlaced systems requiring extended precision pixels are nonsupported with a single device, since the L7:0 inputs are then use for the least significant 8 bits, and the IP7:0 inputs for any more significant bits. If the X15 pin is left open circuit, an internal pullup will configure the device in the host supported mode. The host must then supply a data strobe and an R/W control line. The X7:0 pins must be connected to the host data bus, and are used to both load and read back register values. The PROG and CE pins may be connected together, and then driven by a host address decode. The output on PC1 , which provides a REPLY to the host, need not be used if the width of the data strobe is greater than the maximum tEXP value given in Fig. 10. The configuration bits 6:4 in register A define the window size, maximum pixel rate, and pixel resolution. Window sizes smaller than the maximum in any configuration are implemented by filling in the window with zero coefficients. Bits 3:0 are irrelevant in the Single mode, as is bit 7 if the gain control is used. The result would be expected to lie in either the bottom 20 bits of the 32-bit result , or possibly in the next 20-bit field displaced by four bits. Register C, bits 5:4, must thus select one of these fields for subsequent use by the gain control. The gain is then adjusted such that the 16 outputs available on pins D15:0 are in fact the 16 most significant bits of the result. The gain needed is application specific, but if too much gain is used the OVR pin will go high to indicate an overflow. Register B, bits 2:1, must be set to select the required method of defining the length of the line delays, and the use of bit 3 is dependent on any external pixel delays before the convolver input. No additional delays are needed on the pixel inputs in a single device system, and register D, bits 4:2, should be reset. The pipeline delay in the DELOP output path should match one of those in Table 6, and is window size dependent. Dual device configurations Two devices, each configured with 8-bit pixels and 8W34D windows, can be used to provide an 838 window at up to 20MHz pixel rates. Fig. 14 shows both the non-interlaced and interlaced arrangements. Video lines containing up to 1024 pixels are possible in both configurations, since each device only needs four line delays. One device is configured as the Master by grounding the MASTER pin; the other then receives control signals in the normal way and has its MASTER and SINGLE pins left open circuit. The internal convolver sum, in the device producing the final result, must be delayed by 4 pixels to match the inherent delay in the expansion output from the other device. This is actually achieved by delaying the pixel inputs to the line stores (register D, bits 3:2, = 01). No additional delay in the expansion input is needed, but the pipeline delay used to produce DELOP must be four clocks greater than that given in Table 6 for a single device. The DELOP output is redundant in one of the two devices. Two devices can also be used to support systems requiring 16bit pixels. With this approach the 1638 multiplication is realised as two 838 operations, with the results added together after the most significant half has been shifted by 8 places to the most significant end. This shift operation is controlled by register D, bit 1. Both convolvers are programmed to contain the same coefficients. The convolved output can theoretically grow to 30 bits, and the appropriate field must be selected before using the gain control. Examples of this operating mode are shown in Fig. 15. Each device must be configured in the same 8-bit pixel operating mode, but the device producing the final result must use the 8 place shift option on its internal sum. 21 PDSP16488A of the pixel are connected to the The least significant 8 bits Master device and the most significant 8 bits are connected to the device producing the final result.. The internal sum in this device must be delayed by four pixels to match the delay in the expansion output from the first device. This is actually achieved by delaying the pixel inputs to the line stores (register D, bits 4:2, = 001). The expansion input needs no additional delay (register D, bits 1:0, = 10). The actual pixel precision can be any number of pixels between 8 and 16, and may be a signed or unsigned number. Any unused, more significant bits, must respectively be either sign extended or be tied low. DELOP must have four additional pipeline delays in order to match the total processing delay. This output can be obtained from either device. Four device systems Four devices, each in the 838 mode, can be used to provide a 16316 window, with 8-bit pixel resolution and 10MHz clock rates. The partial sum from the first device in each row must be delayed by eight pixel clocks before it is added to the result from the next device. This provides the eight pixel displacement to match the width of the window. The delay is actually provided by four additional delays in the expansion input to the next device, plus the inherent four clock delays in outputting results from the first device. Register D, bit 0 controls the additional delay. The internal convolver sums, in the two devices in the second row, must be delayed by 12 clocks before they are added to the result from the first row. This twelve clock delay is necessary because of the combination of the eight pixel horizontal displacement delay, and the four clock delay in outputting the result from the last device in the top row. It is actually achieved by delaying the pixel inputs to the line stores (register D, bits 3:2, = 11). The DELOP output must have 20 delays additional to those in a single device. This compensates for the twelve delays added to the convolver sums in the second row, plus an additional eight delays to compensate for the partial width of the first device in the second row. Four devices can also be used to give an 838 window, but with a 30MHz pixel clock. Each device is configured to provide a 434 partial window, but the maximum pixel rate is reduced from 40 to 30MHz because of the response of the line delay expansion circuitry. Intermediate precision is restricted to 16 bits, since time multiplexed data outputs cannot be used above 20MHz. This configuration requires no additional delay in the expansion inputs, and the inputs to the line stores both devices in the second row must be delayed by 8 clock cycles (register D, bits 3:2, = 10). The DELOP output needs twelve additional clock delays to match the processing delay. Figs. 16 and 17 show non-interlaced and interlaced versions of the above 838 and 434 arrangements Fig. 18 shows how four devices can also be used to provide an 838 window, with 16-bit pixels and 20MHz clock rates. The expansion data from a previous device needs no additional delay since the partial window size in each device is only 434. The internal convolver sums from third and fourth devices must be delayed by 8 clocks and the DELOP output must have 12 additional delays. If this arrangement is to be used in a noninterlaced application, the field store must be replaced by four line delays. Six device systems As shown in Fig. 19, six devices, each in an 8W34D mode using 8-bit pixels, can provide a 16W312D window at 20MHz clock rates. Expansion inputs from previous devices in a row (but not the first device in each row) need an extra 4 clocks of delay since the partial window is eight pixels wide. Internal convolver sums need a differential delay of 12 clock cycles from row to row (register D, bits 3:2, = 11). The DELOP output must have 32 additional delays to match the total processing delay. Eight device systems Two additional chips will extend the above six device configuration to a 16316 window. Internal convolver sums must have differential delays of 12 clock cycles between rows, as in the six device system. The DELOP output needs 44 additional clock delays. Nine device systems Nine devices each in the 838 mode will provide a 24324 window with 8- bit data and 10MHz pixel clocks. This is shown in Fig. 20. Expansion data inputs from previous devices in a row (but not the first device in each row) need an extra 4 clocks of delay, controlled by register D, bit 0 The internal convolver sums need differential delays of 20 clock cycles between rows. Sixteen of the latter delays can be provided internally by setting register B, bit 3 and also register D, bits 3:2. The four extra delays must be provided externally. The DELOP output needs 56 clock delays in addition to the 29 required for the 838 single device configuration. 22 PDSP16488A EPROM ADDR DATA VDD 15k NOM VDD 15k NOM GND GND EPROM ADDR DATA VDD 15k NOM VDD 15k NOM GND GND R/W X7:0 R/W X14:8 X14:8 X7:0 X15 X15 DS PROG CE RES CHANGE COEFFS RESET BIN DATA OUT DELAYED SYNC OUTPUT ENABLE PIXEL DATA FIELD DELAY SYNC ODD FIELD DS PROG CE RES CHANGE COEFFS RESET BIN DATA OUT DELAYED SYNC OUTPUT ENABLE SYNC VDD PIXEL DATA LEAST SIG BYTE OF 16-BIT PIXEL HRES BYPASS IP7:0 HRES BYPASS IP7:0 PDSP16488A MASTER SINGLE BIN D15:0 DELOP OEN PDSP16488A MASTER SINGLE BIN D15:0 DELOP OEN OVR L7:0 L7:0 PIXEL CLOCK PIXEL CLOCK OVERFLOW OVERFLOW O/C OVR CLK CLK GND Non-interlaced EPROM mode Interlaced EPROM mode STROBE REPLY REPLY ADDR ADDR DATA O/C O/C R/W X14:8 X7:0 R/W X14:8 X7:0 DS DATA R/W R/W ADDRESS DECODE STROBE DS HOST CPU HOST CPU GND O/C ADDRESS DECODE PROG CE RES RESET BIN DATA OUT DELAYED SYNC OUTPUT ENABLE PC1 X15 PC1 PROG CE RES RESET BIN DATA OUT DELAYED SYNC OUTPUT ENABLE PIXEL DATA FIELD DELAY SYNC ODD FIELD SYNC VDD PIXEL DATA LEAST SIG BYTE OF 16-BIT PIXEL HRES BYPASS IP7:0 HRES BYPASS IP7:0 PDSP16488A MASTER SINGLE BIN D15:0 DELOP OEN X15 PDSP16488A MASTER SINGLE BIN D15:0 DELOP OEN OVR L7:0 L7:0 O/C OVR CLK CLK PIXEL CLOCK OVERFLOW PIXEL CLOCK OVERFLOW GND Non-interlaced 16-bit Host loaded Interlaced 16-bit Host loaded Fig. 13 Single device systems GND O/C 23 PDSP16488A EPROM ADDR DATA MSB VDD 15k NOM GND X14:8 X7:0 X15 8-BIT PIXEL DATA GND SYNC PIXEL CLOCK RESET CLK RES CS0 IP7:0 PC0 R/W HRES PROG CE PDSP16488A 834 WINDOW MASTER SINGLE RES DELAYED SYNC VDD BYPASS CLK DELOP OEN GND PC0 L7:0 DS D15:0 PC1 O/C X14:8 X15 DS 15k NOM X7:0 GND VDD PROG CE IP7:0 PC1 HRES GND R/W SINGLE CLK PDSP16488A 834 WINDOW MASTER RES D15:0 BIN OVR OEN DATA OUT BIN OVERFLOW OUTPUT ENABLE GND O/C BYPASS L7:0 O/C STROBE Non-interlaced R/W REPLY HOST CPU ADDR DATA O/C ADDRESS DECODE O/C X14:8 X7:0 X15 DS PROG CE IP7:0 R/W SYNC ODD FIELD PIXEL CLOCK RESET CLK RES FIELD DELAY O/C HRES BYPASS SINGLE CLK PDSP16488A 834 WINDOW MASTER RES DELAYED SYNC DELOP OEN GND PC0 L7:0 D15:0 PC1 O/C X14:8 X15 X7:0 GND DS 8-BIT PIXEL DATA PC1 IP7:0 HRES R/W PROG CE READ REGISTERS (TRISTATE ENABLE) D7:0 DATA OUT BIN OVERFLOW OUTPUT ENABLE PDSP16488A 834 WINDOW MASTER SINGLE RES D15:0 BIN OVR OEN O/C L7:0 CLK VDD BYPASS O/C Interlaced Fig. 14 8-bit dual device systems 24 O/C PDSP16488A EPROM ADDR DATA MSB VDD 15k NOM GND X14:8 X7:0 X15 16-BIT PIXEL DATA GND SYNC PIXEL CLOCK RESET CLK RES CS0 IP7:0 PC0 R/W HRES PROG CE PDSP16488A 834 WINDOW MASTER SINGLE RES DELAYED SYNC VDD O/C BYPASS CLK DELOP OEN GND PC0 L7:0 DS D15:0 PC1 O/C X14:8 X15 DS 15k NOM X7:0 GND VDD MSB IP7:0 PC1 HRES GND R/W PROG CE PDSP16488A 834 WINDOW MASTER SINGLE RES D15:0 BIN OVR OEN DATA OUT BIN OVERFLOW OUTPUT ENABLE O/C L7:0 CLK STROBE GND BYPASS O/C Non-interlaced R/W REPLY HOST CPU ADDR DATA O/C ADDRESS DECODE O/C X14:8 X7:0 X15 DS LSB IP7:0 R/W SYNC ODD FIELD PIXEL CLOCK RESET CLK RES LSB HRES BYPASS SINGLE PROG CE PDSP16488A 834 WINDOW MASTER RES DELAYED SYNC DELOP OEN GND PC0 L7:0 CLK D15:0 PC1 O/C X14:8 X15 X7:0 GND DS PC1 MSB FIELD DELAY 16-BIT PIXEL DATA VDD MSB IP7:0 HRES R/W PROG CE D7:0 READ REGISTERS (TRISTATE ENABLE) PDSP16488A 834 WINDOW MASTER SINGLE RES D15:0 BIN OVR OEN DATA OUT BIN OVERFLOW OUTPUT ENABLE L7:0 CLK BYPASS O/C Interlaced Fig. 15 Dual device 16-bit systems. O/C 25 PDSP16488A HOST CPU STROBE ADDR DATA R/W REPLY ADDRESS DECODE R/W PIXEL DATA PIXEL CLOCK SYNC RESET CLK HRES RES IP7:0 DS R/W HRES DS PROG CE1 CE2 CE3 CE4 O/C D15:0 D15:0 X14:8 X14:8 X7:0 X7:0 X15 X15 IP7:0 PC1 PC0 DS CE1 R/W HRES PROG CE RES PC1 MASTER PDSP16488A (1) MASTER SINGLE PDSP16488A (2) MASTER SINGLE PROG CE RES CE2 VDD BYPASS CLK OEN L7:0 O/C O/C GND GND O/C GND OEN CLK L7:0 VDD BYPASS DELOP DELAYED SYNC DATA OUT D15:0 D15:0 X14:8 X14:8 X7:0 X7:0 X15 X15 IP7:0 PC0 DS R/W HRES IP7:0 BIN PC1 PROG BIN PC1 PC0 DS PDSP16488A (3) MASTER SINGLE PROG CE RES CE3 R/W HRES PDSP16488A (4) MASTER SINGLE CE RES OVR OEN CE4 OVERFLOW OUTPUT ENABLE OEN CLK GND L7:0 L7:0 GND O/C O/C CLK BYPASS GND BYPASS O/C Fig. 16 Four device non-interlaced system. 26 O/C PDSP16488A VDD 15k NOM EPROM UPPER ADDR BITS ADDR DATA ALS138 CE2 CE3 CE4 PIXEL DATA PIXEL CLOCK SYNC RESET CLK HRES GND D15:0 X14:8 X7:0 CS0 CS1 PC0 X15 VDD D15:0 PC1 PROG CE RES CE2 DELOP X14:8 SINGLE RES IP7:0 PC0 DS IP7:0 DS PC1 GND VDD R/W HRES MASTER PDSP16488A (1) MASTER SINGLE PROG GND RES R/W HRES PDSP16488A (2) MASTER OEN O/C O/C GND GND O/C GND FIELD DELAY OEN CLK CLK BYPASS CE O/C VDD BYPASS X7:0 X15 15k NOM DELAYED SYNC DATA OUT D15:0 D15:0 X14:8 X14:8 X7:0 X7:0 X15 X15 IP7:0 PC0 DS IP7:0 PC1 PC0 DS CE3 PROG CE RES BIN PC1 PROG BIN GND R/W HRES PDSP16488A (3) MASTER SINGLE GND R/W HRES PDSP16488A (4) MASTER SINGLE CE RES OVR OEN CE4 OVERFLOW OUTPUT ENABLE OEN CLK O/C O/C CLK ODD FIELD BYPASS BYPASS O/C Fig. 17 Four device interlaced system. GND O/C 27 PDSP16488A HOST CPU STROBE ADDR DATA R/W REPLY ADDRESS DECODE R/W 16-BIT PIXEL DATA PIXEL CLOCK SYNC RESET CLK HRES RES MSB DS PROG CE1 CE2 CE3 CE4 O/C D15:0 D15:0 PC1 PROG CE RES CE2 DELOP X14:8 X14:8 SINGLE X7:0 IP7:0 DS R/W HRES IP7:0 PC1 PC0 DS CE1 R/W HRES PROG CE RES MASTER PDSP16488A (1) MASTER SINGLE PDSP16488A (2) MASTER VDD LSB BYPASS OEN L7:0 O/C O/C GND GND O/C LSB FIELD DELAY GND OEN CLK CLK L7:0 VDD BYPASS X7:0 X15 X15 MSB DELAYED SYNC MSB DATA OUT D15:0 D15:0 X14:8 X14:8 X7:0 X7:0 PC0 X15 X15 MSB IP7:0 IP7:0 PC1 PC0 DS CE3 R/W HRES PROG CE RES BIN PC1 PROG BIN DS R/W HRES ODD FIELD LSB PDSP16488A (3) MASTER SINGLE PDSP16488A (4) MASTER SINGLE CE RES OVR OEN CE4 OVERFLOW OUTPUT ENABLE OEN CLK L7:0 L7:0 O/C O/C CLK BYPASS BYPASS O/C LSB Fig. 18 Four device system with 16-bit pixels 28 GND O/C PDSP16488A EPROM UPPER ADDR BITS VDD 15k NOM ALS138 ADDR DATA CE2 CE3 CE4 CE5 CE6 PIXEL DATA PIXEL CLOCK SYNC RESET CLK O/C D15:0 X14:8 X7:0 PC0 X15 CS0 CS1 CS2 VDD D15:0 PC1 PROG CE RES CE2 DELOP X14:8 SINGLE RES IP7:0 DS IP7:0 PC0 DS PC1 GND VDD R/W HRES MASTER PDSP16488A (1) MASTER SINGLE PROG CE RES O/C GND VDD R/W HRES PDSP16488A (2) MASTER OEN L7:0 L7:0 O/C O/C GND GND O/C D15:0 IP7:0 PC0 DS IP7:0 PC1 PC0 DS CE3 PROG CE RES D15:0 X14:8 X14:8 X7:0 X7:0 X15 X15 GND OEN CLK CLK BYPASS BYPASS X7:0 X15 HRES 15k NOM DELAYED SYNC PC1 PROG GND GND R/W HRES PDSP16488A (3) MASTER SINGLE GND GND R/W HRES PDSP16488A (4) MASTER SINGLE CE RES CE4 OEN CLK L7:0 L7:0 O/C O/C O/C GND O/C GND OEN CLK BYPASS BYPASS DATA OUT D15:0 D15:0 X14:8 X14:8 X7:0 X7:0 X15 X15 IP7:0 PC0 DS IP7:0 PC1 PC0 DS CE5 PROG CE RES BIN PC1 PROG BIN GND GND O/C R/W HRES PDSP16488A (5) MASTER SINGLE GND GND O/C R/W HRES PDSP16488A (6) MASTER SINGLE CE RES OVR OEN CE6 OVERFLOW OUTPUT ENABLE OEN CLK L7:0 L7:0 O/C O/C CLK BYPASS BYPASS O/C Fig. 19 Six device non-interlaced system. GND O/C 29 PDSP16488A PIXEL CLOCK SYNC RESET PIXEL DATA CLK HRES RES EPROM UPPER ADDRESS BITS VDD DECODE 15k NOM VDD 15k NOM ADDR DATA CE2 CE3 CE4 CE5 CE6 CE7 CE8 CE9 PROG DS O/C D15:0 D15:0 IP7:0 IP7:0 PC1 PC0 DS CE2 GND VDD R/W HRES PROG CE RES IP7:0 DS GND VDD R/W HRES CS3 D15:0 PC1 PROG CE RES CE3 X14:8 X14:8 X14:8 SINGLE O/C X7:0 X7:0 MASTER PDSP16488A (1) MASTER SINGLE PC1 PROG CE O/C GND VDD PC0 DS R/W PDSP16488A (2) MASTER SINGLE PDSP16488A (3) MASTER O/C X7:0 OEN OEN L7:0 BYPASS O/C O/C GND GND O/C GND 4 CLK DELAYS D15:0 D15:0 IP7:0 IP7:0 PC1 PC0 DS CE4 GND R/W HRES PROG CE RES IP7:0 PC1 PC0 DS CE5 GND GND R/W HRES PROG CE RES D15:0 PC1 PROG CE RES CE6 X14:8 X14:8 DS GND GND R/W HRES PDSP16488A (4) MASTER SINGLE PDSP16488A (5) MASTER SINGLE PDSP16488A (6) MASTER O/C SINGLE OEN CLK OEN L7:0 4 CLK DELAYS O/C O/C O/C O/C GND GND O/C GND OEN CLK CLK BYPASS GND BYPASS BYPASS X14:8 X7:0 X7:0 PC0 X15 X15 X15 GND OEN CLK CLK CLK BYPASS RES HRES BYPASS X7:0 CS0 CS1 CS2 X15 PC0 X15 X15 DATA OUT D15:0 D15:0 D15:0 X14:8 X14:8 X14:8 X7:0 X7:0 X7:0 X15 PC0 X15 X15 IP7:0 IP7:0 PC1 PC0 DS CE7 GND R/W HRES PROG CE RES IP7:0 PC1 PC0 DS CE8 GND GND R/W HRES BIN PC1 DS GND GND O/C R/W HRES PDSP16488A (7) MASTER SINGLE PDSP16488A (8) MASTER SINGLE PROG CE RES PDSP16488A (9) MASTER SINGLE PROG CE RES OVR OEN OVERFLOW OUTPUT ENABLE CE9 OEN CLK OEN CLK L7:0 O/C O/C O/C O/C CLK BYPASS GND BYPASS DELOP BYPASS O/C GND Fig. 20 Nine device non-interlaced system 30 GND DELAYED SYNC O/C For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. 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